Staff Engineer, ASIC Development Engineering (SOC Design)

About the Role:

We are seeking a highly experienced and motivated Principal Engineer specialising in SoC RTL Design for System-on-Chip (SoC) solutions. As a key technical skill, you will drive the SoC Architecture, Design, and integration of complex digital systems, collaborating with cross-functional teams to deliver next-generation semiconductor products.

Key Responsibilities:

Define and review SoC architecture and design specifications.

Develop high-quality RTL which is synthesizable using Verilog/SystemVerilog.

Ensure robust design methodologies, including lint, CDC, RDC and FC-Elab.

Drive Cross-Functional Collaboration: Partner with SoC Design, Verification, Validation, DFT, Physical Design, Mixed-Signal IP, Foundry, Hardware, Firmware, and Test Engineering

Mentor and Inspire: Provide technical leadership and mentorship to engineering teams, fostering a culture of innovation, accountability, and continuous improvement.

Technical Excellence: Drive integration and debug efforts for subsystem and full-chip level. Analyse design trade-offs and guide design optimisations for area, performance, and power.

Contribute to IP selection, evaluation, and integration in SoC designs.

Communicate with Impact: Deliver clear, concise, and transparent project updates to stakeholders, ensuring alignment across all levels.

Required Skills & Experience

Bachelor’s or Master’s degree in Electrical/Electronic Engineering or related field.

5–8 years of experience in digital design, with a strong focus on RTL design and integration for complex SoCs.

Hands-on experience in SoC integration, including subsystem and top-level integration.

Deep expertise in Verilog/SystemVerilog.

Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug.

Experience with synthesis, static timing analysis, and DFT concepts.

Proficiency with EDA tools (simulation, lint, CDC, synthesis, formal verification, LEC).

Experience with version control systems (Perforce/Git) and collaborative development flows.

Excellent analytical, problem-solving, and communication skills.

Strong ownership, ability to work independently, and passion for delivering high-quality, scalable solutions

Preferred Expertise:

Experience with high-speed interfaces (PCIe, LPDDR5, High Speed Memories etc.).

Expertise in low-power design techniques and high-speed interfaces.

Familiarity with scripting languages (Perl, Python, TCL, Shell) for design automation and flow customisation.

Experience with silicon bring-up, post-silicon validation, and debug.

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