Technologist, ASIC Development Engineering (STA, Sign-Off)

Position Overview:

We are seeking an exceptionally skilled and strategic Technologist for our Static Timing Analysis (STA) function. The successful candidate will serve as a technical leader and subject matter expert, guiding a team of talented engineers and driving innovation in timing closure methodologies for our most complex semiconductor designs. This role demands deep expertise in STA, proven leadership in cross-functional collaboration, architectural thinking, and the ability to influence technical direction across multiple projects and organizations.

Key Responsibilities:

- Lead a team of talented STA engineers , observe complete ownership of ASIC timing signoff across , fostering technical growth, and building a high-performing organization capable of delivering excellence in timing closure for complex semiconductor designs.

- Architect and define organization-wide STA methodology and standards, establishing best practices, signoff frameworks, and quality metrics that enable consistent, scalable timing closure across all ASIC projects and process nodes.

- Work with IP & Design team for Timing constraints Development & Review activities.

- Develop and implement advanced STA methodologies and strategies to meet the timing closure requirements of complex IC designs.

- Collaborate with cross-functional teams, including design, verification, physical design, and DFT, to ensure seamless integration and optimal timing performance.

- Conduct thorough timing analysis, identify critical paths, and develop strategies to mitigate timing violations and improve overall design performance.

- Stay abreast of industry trends and emerging technologies in STA and related fields, and incorporate best practices into the team’s workflow.

- Prepare and present detailed timing reports and technical documentation to stakeholders

- Foster a culture of innovation, collaboration, and continuous improvement within the STA team.

- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.

- A minimum of 13 years of experience in Static Timing Analysis.

- Proven leadership experience managing and developing STA engineering teams

- Demonstrated track record of complete timing signoff ownership on multiple successful tape-outs in advanced process nodes

- Expert-level knowledge of industry-standard STA tools (Synopsys PrimeTime, Cadence Tempus, etc.)

- Deep understanding of advanced timing concepts: MMMC, OCV, AOCV, POCV, SI analysis, power-aware timing

- Strong scripting expertise (TCL, Python, Perl) and experience with automation frameworks

- Exceptional leadership and people management skills with ability to build and scale high-performing teams

- Excellent communication and influence skills with ability to engage at all organizational levels

- A proactive, results-oriented mindset with a passion for innovation and continuous improvement.

- Experience with advanced process nodes (e.g. 5nm, 3nm) is highly desirable.

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